Curriculum/cache-coherence
Cache Coherence
memory model·L1 · combinator·stub
Replacesthe belief that an atomic operation is 'free' compared to a mutex.
Both atomic RMW and mutex acquire invalidate the cache line that other cores hold; the contention cost is the coherence traffic the protocol (MESI / MOESI) must replay, not the synchronisation primitive's instruction count. Same line, same bus, same cost.
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Author at: content/concepts/cache-coherence/card.ts