ST
StateTrace
Visual Quant & Low-Latency Systems Lab
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Concepts/Synchronization/Race Condition

Race Condition

The same read–compute–write bug class in three domains. Bank balance loses a withdrawal. Lazy initialization leaks an allocation. Ticket booking double-books a seat. Same shape, different surface.

Steps
1/12
Stateshared + per-thread
T1
T1 local
statusidle
balance
new_balance
amount
shared
shared memoryread
balance100
counter per stepnow = 100
T2
T2 local
statusidle
balance
new_balance
amount
Race conditions are a bug class. Correctness, not latency, is the measurement.
OBSERVED

shared.balance = 100. Both worker threads are idle, waiting for a withdraw call.

Bank Balance
1account = {"balance": 100}
2
3def withdraw(amount):
4    balance = account["balance"]       # read
5    new_balance = balance - amount     # compute
6    account["balance"] = new_balance   # write
Historystep 1 / 12
step 1/12
Same race shape, different surface. Walk the other two for the full pattern.